用于重新定時(shí)串行發(fā)送數(shù)據(jù)的發(fā)射器參考時(shí)鐘,是為接收器路徑恢復(fù)時(shí)鐘的延遲拷貝。一個(gè)數(shù)據(jù)FIFO能使發(fā)射器并行時(shí)鐘與串行時(shí)鐘不相同。然后您可以手動調(diào)整串行發(fā)送數(shù)據(jù)至串行接收數(shù)據(jù)的相位關(guān)系,以便測量串?dāng)_。BERT直接由接收器路徑中的一個(gè)外部16:1復(fù)用器驅(qū)動,從而當(dāng)接收器遭受發(fā)射器的串?dāng)_時(shí),您就能獨(dú)立于發(fā)射器路徑來測量接收器的BER。
當(dāng)串行發(fā)送數(shù)據(jù)延遲相對于串行接收數(shù)據(jù)從0至100皮秒變化時(shí),所得BER也隨之發(fā)生變化（圖8）。在25°C及更高的70°C下進(jìn)行測量,可得到相似的結(jié)果。在BER為10-4（或10kb 中有一個(gè)錯(cuò)誤）的情況下,BER變化幅度為5左右。這種BER變化在光域中近似于0.3dB的靈敏度惡化。
參考文獻(xiàn)
1. Rayas-Sanchez, JE, "A Frequency-Domain Approach to Interconnect Crosstalk Simulation and Minimization," Department of Electronics, Systems, and Informatics, ITESO University, Tlaquepaque, Jalisco, Mexico.
2. Vittal, A, LH Chen, M Marek-Sadowska, K Wang, and S Yang, "Crosstalk in VLSI Interconnections," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 18, No. 12, pg 1817, December 1999.
3. Chou, H, and S Chiu, "Crosstalk Reduction and Tolerance in Deep Sub-Micron Interconnects," Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI.
4. Bockelman, DE and WR Eisenstadt, "Direct Measurement of Crosstalk Between Integrated Differential Circuits," IEEE Transactions on Microwave Theory and Techniques, Volume 48, No. 8, August 2000, pg 1410.
5. Johnson, H and M Graham, High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall PTR: Upper Saddle River, NJ, 1993, pg 189.
