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;**************************] ;MCU:W78E51(MCS-51 系列單片機(jī)) CS BIT P0.0 WRI BIT P0.2 DATA_BIT BIT P0.1 ;30H~32H are used for write cycle flag ;40H~43H are used for delay sub-program ORG 0000H START: INIT: CLR CS MOV A,#10000000B ;select command writing LCALL MODE_SELECT ;sub_program for command mode or data mode selection MOV A,#01H ;system oscillator on LCALL WCOM MOV A,#03H ;display on LCALL WCOM MOV A,#29H ;set bias=1/3; duty=1/4 LCALL WCOM SETB CS MAIN: lcall kenwood lcall waitkey LJMP START clear: setb cs ;these two rows are important clr cs MOV a,#0a0h lcall mode_select MOV a,#00h lcall address MOV r0,#017 clear1: MOV a,#00h lcall wdata djnz r0,clear1 ret kenwood: setb cs clr cs MOV a,#0a0h lcall mode_select MOV a,#00h lcall address MOV a,#040h lcall wdata kenwood_1: setb cs clr cs MOV a,#0a0h lcall mode_select MOV a,#0 lcall address MOV r1,#32 MOV dptr,#data_kenwood kenwood_2: MOV a,#0 MOVc A,@a+dptr lcall wdata inc dptr djnz r1,kenwood_2 ret MODE_SELECT: MOV 33H,#03H MODE_SELECT1: CLR WRI RLC A MOV DATA_BIT,C LCALL DELAY_1MS SETB WRI DJNZ 33H,MODE_SELECT1 RET WCOM: ;write command to ht1621 MOV 30H,#8 WCOM2: CLR WRI RLC A MOV DATA_BIT,C LCALL DELAY_1MS SETB WRI DJNZ 30H,WCOM2 CLR WRI ; CLR DATA_BIT LCALL DELAY_1MS SETB WRI RET ADDRESS: ;write address to ht1621 RLC A RLC A MOV 31H,#6 ADD1: CLR WRI RLC A MOV DATA_BIT,C LCALL DELAY_1MS SETB WRI DJNZ 31H,ADD1 RET WDATA: ;write data to ht1621 MOV 32H,#4 WDATA1: CLR WRI RLC A MOV DATA_BIT,C LCALL DELAY_1MS SETB WRI DJNZ 32H,WDATA1 RET WAITKEY:SETB P2.0 ;wait a key to next screen MOV 43H,#80 WAITKEY1: LCALL DELAY ;IN ORDER TO ACCEPT SELECT STATUS DJNZ 43H,WAITKEY1 STATUS: MOV C,P2.0 JC STATUS RET
WAIT: MOV 42,#2FH WAIT0: LCALL DELAY DJNZ 42,WAIT0 RET ;DELAY SUBPROGRAM DELAY: MOV 40H,#032H ;10.05ms DELAY1: MOV 41H,#030H DELAY2: DJNZ 41H,DELAY2 ;192us DJNZ 40H,DELAY1 RET DELAY_1MS: MOV 44H,#005H DELAY_1MS1: MOV 45H,#030H DELAY_1MS2: DJNZ 45H,DELAY_1MS2 DJNZ 44H,DELAY_1MS1 RET data_kenwood: db 0C0h,0E0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h db 0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h,0F0h END |