At89c2051 Successive Approximation A-to-D conversionNAME SA_ADC_Test; Test program to loop on Successive Approximation A-to-D conversion.; Allows digital codes and resulting DAC output to be viewed on 'scope. DSEG AT 0020H ORG 0060H ; stack originstack: DS 0020H ; stack depth CSEG ORG 0000H ; power on/reset vector jmp on_reset ORG 0003H ; external interrupt 0 vector reti ; undefined ORG 000BH ; timer 0 overflow vector reti ; undefined ORG 0013H ; external interrupt 1 vector reti ; undefined ORG 001BH ; timer 1 overflow vector reti ; undefined ORG 0023H ; serial I/O interrupt vector reti ; undefined ORG 0040H ; begin constant data space ORG 0080H ; begin code space USING 0 ; register bank zeroon_reset: mov sp, #(stack-1) ; initialize stack pointer mov IE, #0 ; deactivate all interrupts mov a, #0ffh ; deactivate output ports mov p1, a ; mov p3, a ; loop: call ADC ; convert sjmp loop ; againADC: ; Convert analog-to-digital. ; Executes a successive approximation algorithm in an attempt to ; find an eight-bit code which causes the DAC output to match the ; unknown voltage at the comparator input. The algorithm returns ; one of 256 values ranging from 00000000 (zero volts) to 11111111 ; (full scale). The exact correspondence between the code and input ; voltage is determined in hardware. ; Before the search begins, zeros are written to the DAC and the ; comparator is checked to verify that its output is low. If it is ; not, a code of zero is returned immediately. If the routine ; completes and the comparator output has never gone high, a code ; of all ones is returned, corresponding to full scale. ; Delays have been inserted to allow for worst case op amp slew rate, ; resulting in a conversion time of approximately 275 microseconds. ; The code is returned in A. All other registers are preserved. push b ; save mov b, r7 ; push b ; mov b, #0 ; first code call DAC ; write DAC nop ; wait for op amp to slew F.S. to zero nop ; plus settling time nop ; total five uS at 12 MHz nop ; nop ; jb p3.6, xxx ; exit if comparator high clr c ; intialize loop counter/bit mask mov a, #10000000b ; aaa: orl b, a ; set bit in DAC code call DAC ; try new code nop ; wait for op amp to slew 1/2 F.S. nop ; plus settling time nop ; total five uS at 12 MHz nop ; nop ; jnb p3.6, bbb ; jump if voltage still low, keep bit xrl b, a ; voltage too high, reset bit bbb: rrc a ; shift loop counter/bit mask jnc aaa ; loop until bit in mask moves into C xxx: mov a, b ; return code in A pop b ; restore mov r7, b ; pop b ; retDAC: ; Write the eight bit code in register B to the DAC. ; The six most significant bits of the code are written to the ; six most significant bits of port one. The two least significant ; bits of the code are written to bits five and four of port three. ; It is assumed that the comparator is in use, so the bits in port ; one corresponding to the comparator inputs are set. ; All unused bits are undisturbed. ; No delays are included for DAC settling or op amp slewing. ; All registers are preserved. push b ; save code orl b, #00000011b ; enable comparator mov p1, b ; write bits seven to two pop b ; restore code mov c, b.1 ; write bit one mov p3.5, c ; mov c, b.0 ; write bit zero mov p3.4, c ; ret END | 
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