The PS/2 mouse and keyboard implement a bidirectional synchronous serial protocol. PS/2鼠標和鍵盤執(zhí)行一個雙向同步串行協(xié)議。
The bus is "idle" when both lines are high (open-collector). 總線空閑時，兩條線都是高電平(集電極開路)。
This is the only state where the keyboard/mouse is allowed begin transmitting data. 在這種狀態(tài)下，鍵盤/鼠標才允許開始傳輸數(shù)據(jù)。
The host has ultimate control over the bus and may inhibit communication at any time by pulling the Clock line low. 主機對總線有最高的控制權，在任何時候通過將時鐘線拉低就可以禁止通信。
The device always generates the clock signal. 時鐘信號總是由設備端生成的。
If the host wants to send data, it must first inhibit communication from the device by pulling Clock low. 如果主機想發(fā)送數(shù)據(jù)，它必須先將時鐘拉低來禁止來自設備端的通信。
The host then pulls Data low and releases Clock. 然后主機再拉低數(shù)據(jù)線，釋放時鐘。 <-- CETagParser ~color=red~ --><-- /CETagParser -->注釋:釋放時鐘，就是再恢復時鐘為高<-- CETagParser ~/color~ --><-- /CETagParser -->
This is the "Request-to-Send" state and signals the device to start generating clock pulses. 這就是"請求發(fā)送(Request-to-Send)"狀態(tài)，提示 設備端 開始生成時鐘信號。
Summary: Bus States Data = high, Clock = high: Idle state. Data = high, Clock = low: Communication Inhibited. Data = low, Clock = high: Host Request-to-Send 總結(jié):總線狀態(tài) 數(shù)據(jù) 0 1
0 ---------通信禁止----------- 時鐘 1 主機要求發(fā)送 總線空閑
The clock and data pins are bidirectional, open-collector signals that are pulled to 5 V by pullup resistors in the keyboard. 時鐘和數(shù)據(jù) 引腳時 雙向 集電極開路的信號，可以被鍵盤內(nèi)部的上拉電阻 拉高到5V
Data sent from the device to the host is read on the falling edge of the clock signal; data sent from the host to the device is read on the rising edge. 從設備發(fā)送給主機的數(shù)據(jù)時在時鐘信號的下降沿讀取的;從主機發(fā)給設備的數(shù)據(jù)是在上升沿讀取的。
The clock frequency must be in the range 10 - 16.7 kHz. This means clock must be high for 30 - 50 microseconds and low for 30 - 50 microseconds.. 時鐘頻率必須在10-16.7KHz之間。這意味著時鐘必須是 高電平持續(xù)30～50毫秒，低電平持續(xù) 30～50毫秒。
If you're designing a keyboard, mouse, or host emulator, you should modify/sample the Data line in the middle of each cell. I.e. 15 - 25 microseconds after the appropriate clock transition. 如果你設計一個鍵盤 鼠標 或者 主機模擬器，你必須 在每個單元的中間時刻 （也就是,在時鐘跳變之后的15～25毫秒后） 修改/取樣數(shù)據(jù)線.
Again, the keyboard/mouse always generates the clock signal, but the host always has ultimate control over communication. 重復一遍，鍵盤/鼠標 總是 生成時鐘信號， 而 主機 控制著整個通信過程。
Timing is absolutely crucial. Every time quantity I give in this article must be followed exactly. 時序是非常重要的。在本文中給出的時間數(shù)必須嚴格遵循。
設備發(fā)送數(shù)據(jù)到主機
The Data and Clock lines are both open collector. 數(shù)據(jù)和時鐘線都是集電極開路的。
A resistor is connected between each line and +5V, so the idle state of the bus is high. 在+5V 和每根線 之間連接著一個電阻，所以 總線的空閑狀態(tài) 是 高電平。
When the keyboard or mouse wants to send information, it first checks the Clock line to make sure it's at a high logic level. 當鍵盤或者鼠標想發(fā)送數(shù)據(jù)時，它首先必須檢查時鐘線 ，確認它處于高電平。
If it's not, the host is inhibiting communication and the device must buffer any to-be-sent data until the host releases Clock. 如果不是，主機禁止通信，設備必須緩沖任何要發(fā)送的數(shù)據(jù)，直到主機釋放時鐘。
The Clock line must be continuously high for at least 50 microseconds before the device can begin to transmit its data. 在設備開始傳輸數(shù)據(jù)之前，時鐘線 必須持續(xù)為 高電平的 時間 必須 至少50ms
The keyboard/mouse writes a bit on the Data line when Clock is high, and it is read by the host when Clock is low. 當時鐘為高電平時，鍵盤/鼠標寫一個bit到數(shù)據(jù)線上；當時鐘為低電平時，主機從數(shù)據(jù)線上讀取這個bit 。
The Data line changes state when Clock is high and that data is valid when Clock is low.
The clock frequency is 10-16.7 kHz. 時鐘頻率是10-16.7KHz
The time from the rising edge of a clock pulse to a Data transition must be at least 5 microseconds. 從時鐘脈沖的上升沿到數(shù)據(jù)跳變 的時間必須至少 5ms
The time from a data transition to the falling edge of a clock pulse must be at least 5 microseconds and no greater than 25 microseconds. 從數(shù)據(jù)跳變 到時鐘脈沖的下降沿 必須 至少5ms,且不超過25ms
The host may inhibit communication at any time by pulling the Clock line low for at least 100 microseconds.
主機可在任何時間禁止通信，只需要將時鐘線下拉位低電平超過100ms即可
If a transmission is inhibited before the 11th clock pulse, the device must abort the current transmission and prepare to retransmit the current "chunk" of data when host releases Clock. 如果在第11個脈沖時禁止傳輸，設備必須中止當前的傳輸，準備重新傳輸當前的數(shù)據(jù)"chunk（塊)"當主機釋放時鐘時
A "chunk" of data could be a make code, break code, device ID, mouse movement packet, etc. 一個數(shù)據(jù)塊可能時 通碼，斷碼，設備ID，鼠標移動包 等等。
For example, if a keyboard is interrupted while sending the second byte of a two-byte break code, it will need to retransmit both bytes of that break code, not just the one that was interrupted. 舉個例子，如果當發(fā)送 一個兩字節(jié)斷碼的 第2個字節(jié)時，鍵盤被中斷，它將需要重新發(fā)送 此斷碼的兩個字節(jié)，而不僅僅時被中斷掉的那個字節(jié)。
If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/mouse does not need to retransmit any data. 如果在第一個 高->低 時鐘跳變 時，（或者在 最后一個時鐘脈沖的下降沿 之后）主機將時鐘拉低，鍵盤/鼠標 不必重新傳輸任何數(shù)據(jù)。
However, if new data is created that needs to be transmitted, it will have to be buffered until the host releases Clock. 但是，如果新產(chǎn)生的數(shù)據(jù)需要傳輸，它必須將數(shù)據(jù)緩沖，知道主機釋放時鐘。
Keyboards have a 16-byte buffer for this purpose. If more than 16 bytes worth of keystrokes occur, further keystrokes will be ignored until there's room in the buffer. 鍵盤有一個16字節(jié)的緩沖區(qū)。如果有超過16個字節(jié)的擊鍵存在，更多的擊鍵將被忽略。直到 緩沖區(qū)有空地。
Mice only store the most current movement packet for transmission. 鼠標只能緩沖最近的一個要傳輸?shù)模ㄒ苿?數(shù)據(jù)包。
<-- CETagParser ~code~ -->
<-- /CETagParser -->時間參數(shù) 最大值/最小值 T1數(shù)據(jù)跳變到時鐘的下降沿 5/25 us T2時鐘的上升沿 到 數(shù)據(jù)跳變 5/T4 - 5 us T3時鐘inactive 30-50 us T4時鐘active 30-50 us T5 >0/50 us<-- CETagParser ~/code~ -->
<-- /CETagParser -->
Time to auxiliary device inhibit after clock 11 to ensure the auxiliary device does not start another transmission
The auxiliary device checks the 'clock' line. If the line is inactive, output from the device is not allowed. 輔助設備(指 鍵盤) 檢查 時鐘線 ，如果時低電平，禁止發(fā)送數(shù)據(jù)
The auxiliary device checks the 'data' line. If the line is inactive, the controller receives data from the system. 設備檢查數(shù)據(jù)線，如果是 低電平，那么控制器從系統(tǒng)接收數(shù)據(jù)
The auxiliary device checks the 'clock' line during the transmission at intervals not exceeding 100 microseconds. If the device finds the system holding the 'clock' line inactive, the transmission is terminated. The system can terminate transmission anytime during the first 10 clock cycles. 設備在傳輸過程中 檢查 時鐘 線 間隔不超過100us。 如果設備發(fā)現(xiàn) 主機系統(tǒng) 將電平拉低，就終止傳輸。 在傳輸過程的前10個時鐘周期的任何時候，主機系統(tǒng)可以中止傳輸。
A final check for terminated transmission is performed at least 5 microseconds after the 10th clock. 終止傳輸?shù)淖詈笠粋�檢查 要持續(xù)至少5us
The system can hold the 'clock' signal inactive to inhibit the next transmission. 系統(tǒng)拉低時鐘線，將禁止下一次傳輸
The system can set the 'data' line inactive if it has a byte to transmit to the device. The 'data' line is set inactive when the start bit (always 0) is placed on the 'data' line. 系統(tǒng)如果有一個字節(jié)要傳輸給設備，可以拉低數(shù)據(jù)線。當開始位（總是0）放置到數(shù)據(jù)線時，數(shù)據(jù)線被拉低。
The system raises the 'clock' line to allow the next transmission. 系統(tǒng)拉高時鐘將允許下一次傳輸
Host-to-Device主機到設備的通信 First of all, the PS/2 device always generates the clock signal. 首先，PS/2設備總是產(chǎn)生時鐘信號
If the host wants to send data, it must first put the Clock and Data lines in a "Request-to-send" state as follows: 如果主機想發(fā)送數(shù)據(jù)，它必須先將時鐘線和數(shù)據(jù)線設置成"Request-to-send"狀態(tài): 1) Inhibit communication by pulling Clock low for at least 100 microseconds. 拉低時鐘線至少100us來禁止通信 2) Apply "Request-to-send" by pulling Data low, then release Clock. 拉低數(shù)據(jù)線，請求 "Request-to-send", 然后釋放時鐘 .
The device should check for this state at intervals not to exceed 10 milliseconds. 設備應該在不超過10ms(注意，是毫秒)的間隔內(nèi)就要檢查一次這個狀態(tài)。
When the device detects this state, it will begin generating Clock signals and clock in eight data bits and one stop bit. 當設備檢測到這個狀態(tài)，它將開始產(chǎn)生時鐘信號，
The host changes the Data line only when the Clock line is low, and data is read by the device when Clock is high. 只有當時鐘線 為低的時候，主機才可以改變數(shù)據(jù)線（也就是將數(shù)據(jù)寫入到數(shù)據(jù)線）。數(shù)據(jù)將在時鐘為高電平的時候 被 設備讀取。
After the stop bit is received, the device will acknowledge the received byte by bringing the Data line low and generating one last clock pulse. 在收到停止位之后，設備將通過拉低數(shù)據(jù)線，生成最后一個時鐘脈沖 來 應答收到的字節(jié)
If the host does not release the Data line after the 11th clock pulse, the device will continue to generate clock pulses until the the Data line is released (the device will then generate an error.) 在第11個時鐘脈沖之后，如果主機并沒有釋放數(shù)據(jù)線，設備將繼續(xù)產(chǎn)生時鐘脈沖，直到數(shù)據(jù)線被釋放（然后 設備將產(chǎn)生一個錯誤）
The host may abort transmission at time before the 11th clock pulse (acknowledge bit) by holding Clock low for at least 100 microseconds. 在第11個脈沖之前（回應位），主機可以隨時中止傳輸，只要拉低時鐘持續(xù)100us即可
<-- CETagParser ~code~ -->
<-- /CETagParser -->時間參數(shù) 最大值/最小值 T7 時鐘低電平 30-50 us T8 時鐘高電平 30-50 us T9 30-50 us<-- CETagParser ~/code~ -->
<-- /CETagParser -->
T9 == Time from inactive to active CLK transition, used to time when the auxiliary device samples DATA
1. 鍵盤發(fā)送數(shù)據(jù)前，首先必須讓時鐘 和數(shù)據(jù)線都在鍵盤內(nèi)部的上拉電阻作用下 拉成高電平。然后鍵盤拉低數(shù)據(jù)線，5－25us之后，鍵盤拉低時鐘線。在時鐘的下降沿，開始傳輸起始位The falling edge of the clock line clocks in the transfer’s start bit.
66821730(技術支持)
