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            end if;  
      end if;
  end process;
  process(reset,txclk)
  variable tsr,tsr1,oddb1,oddb2: std_logic_vector(7 downto 0);
   begin
         if reset='1' then
            txcnt_r<=(others=>'0');
                 sout1<='1';
                    state<=start1;                    
                       cou<=0;
         elsif txclk'event and txclk='1' then                 
         case state is
         when start1=>
              if start='1' then            
                 if cou=3 then
                    len<=thr;
                 end if;
                 tsr:=thr(7 downto 0);
     oddb1:=thr(7 downto 0); 
                 sout1<='0'; --起始位 
                 txcnt_r<=(others=>'0');   
                 state<=shift1;
              else
                 state<=start1;
              end if;
         when shift1=>
              oddb<=oddb1(7) xor oddb1(6) xor oddb1(5) xor oddb1(4) xor oddb1(3) xor oddb1(2) xor oddb1(1) xor oddb1(0);
              sout1<=tsr(0); --數(shù)據(jù)位